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acpl-p343 and acpl-w343 4.0 amp output current igbt gate drive optocoupler with rail-to-rail output voltage in stretched so6 data sheet caution: it is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by esd. description the acpl-p343/w343 contains an algaas led, which is optically coupled to an integrated circuit with a power output stage. this optocoupler is ideally suited for driving power igbts and mosfets used in motor control inverter applications. the high operating voltage range of the output stage provides the drive voltages required by gate controlled devices. the voltage and high peak output current supplied by this optocoupler make it ideally suited for direct driving igbt with ratings up to 1200 v / 200 a. for igbts with higher ratings, this optocoupler can be used to drive a discrete power stage which drives the igbt gate. the acpl-p343 and acpl-w343 have the highest insulation voltage of v iorm = 891 v peak and v iorm = 1140 v peak respectively in the iec/en/din en 60747-5-2. functional diagram note: a 1 ? f bypass capacitor must be connected between pins v cc and v ee . features ?? 4.0 a maximum peak output current ?? 3.0 a minimum peak output current ?? rail-to-rail output voltage ?? 200 ns maximum propagation delay ?? 100 ns maximum propagation delay diff erence ?? led current input with hysteresis ?? 35 kv/ ? s minimum common mode rejection (cmr) at v cm = 1500 v ?? i cc = 3.0 ma maximum supply current ?? under voltage lock-out protection (uvlo) with hysteresis ?? wide operating v cc range: 15 to 30 v ?? industrial temperature range: -40 c to 105 c ?? safety approval: C ul recognized 3750/5000 v rms for 1 min. C csa C iec/en/din en 60747-5-2 v iorm = 891/1140 v peak applications ?? igbt/mosfet gate drive ?? ac and brushless dc motor drives ?? renewable energy inverters ?? industrial inverters ?? switching power supplies truth table led v cc C v ee positive going (i.e., turn-on) v cc C v ee negative going (i.e., turn-off) v o off 0 C 30 v 0 C 30 v low on 0 C 12.1 v 0 C 11.1 v low on 12.1 C 13.5 v 11.1 C 12.4 v transition on 13.5 C 30 v 12.4 C 30 v high v cc v ee 1 2 3 6 5 4 cathode nc anode v out cathode nc anode
2 ordering information acpl-p343 is ul recognized with 3750 v rms for 1 minute per ul1577. acpl-w343 is ul recognized with 5000 v rms for 1 minute per ul1577. part number option package surface mount tape & reel iec/en/din en 60747-5-2 quantity rohs compliant acpl-p343 acpl-w343 -000e stretched so-6 x 100 per tube -500e x x 1000 per reel -060e x x 100 per tube -560e x x x 1000 per reel to order, choose a part number from the part number column and combine with the desired option from the option column to form an order entry. example 1: acpl-p343-560e to order product of stretched so-6 surface mount package in tape and reel packaging with iec/en/ din en 60747-5-2 safety approval in rohs compliant. example 2: acpl-w343-000e to order product of stretched so-6 surface mount package in tube packaging and rohs compliant. option datasheets are available. contact your avago sales representative or authorized distributor for information.
3 package outline drawings acpl-p343 stretched so-6 package (7 mm clearance) acpl-w343 stretched so-6 package (8 mm clearance) 7 7 45 5 no m. 0. 3 81 0.1 2 7 (0.01 5 0.00 5 ) 1. 2 7 (0.0 5 0) bsg 4 . 5 80 + 0. 254 C 0 7 7 3 .180 0.1 2 7 (0.1 25 0.00 5 ) 1. 5 90 0.1 2 7 (0.0 63 0.00 5 ) 0. 254 0.0 5 0 (0.010 0.00 2 ) 9.7 0. 25 0 (0. 3 8 2 0.010) floating lead protusions max. 0.25 (0.01) dimensions in millimeters (inches) lead coplanarity = 0.1 mm (0.004 inches) 0.180 + 0.010 C 0.000 () 1 0. 25 0 (0.0 4 0 0.010) 0. 2 0 0.10 (0.008 0.00 4 ) 7. 62 (0. 3 00) 6 .81 (0. 26 8) 0. 45 (0.018) 10.7 (0. 42 1) 1. 2 7 (0.0 5 ) 0.7 6 (0.0 3 ) 2 .1 6 (0.08 5 ) land pattern recommendation 45 7 7 2 1 34 5 6 7 7 0. 3 81 0.1 2 7 (0.01 5 0.00 5 ) 0. 2 0 0.10 (0.008 0.00 4 ) floating lead protusions max. 0.25 (0.01) dimensions in millimeters (inches) lead coplanarity = 0.1 mm (0.004 inches) 4 . 5 80 + 0. 254 C 0 0.180 + 0.010 C 0.000 () 6 .807 + 0.1 2 7 C 0 0. 26 8 + 0.00 5 C 0.000 () 1. 2 7 (0.0 5 0) bsg 35 no m. 0.7 5 0 0. 25 0 (0.0 2 9 5 0.010) 11. 5 00 0. 25 (0. 453 0.010) 0. 254 0.0 5 0 (0.010 0.00 2 ) 1. 5 90 0.1 2 7 (0.0 63 0.00 5 ) 3 .180 0.1 2 7 (0.1 25 0.00 5 ) 0. 45 (0.018) 7. 62 (0. 3 00) 1 2 . 65 (0. 5 ) 1. 2 7 (0.0 5 ) 0.7 6 (0.0 3 ) 1.90 5 (0.07 5 ) land pattern recommendation
4 recommended pb-free ir profi le recommended refl ow condition as per jedec standard, j-std-020 (latest revision). non- halide flux should be used. regulatory information the acpl-p343/w343 is approved by the following organizations: ul recognized under ul 1577, component recognition program up to v iso = 3750 v rms (acpl-p343) and v iso = 5000 v rms (acpl-w343) expected prior to product release. csa csa component acceptance notice #5, file ca 88324 iec/en/din en 60747-5-2 (option 060 only) maximum working insulation voltage v iorm = 891 v peak (acpl-p343) and v iorm = 1140 v peak (acpl-w343) table 1. iec/en/din en 60747-5-2 insulation characteristics* (option 060 C under evaluation) description symbol acpl-p343 option 060 acpl-w343 option 060 unit installation classifi cation per din vde 0110/1.89, table 1 for rated mains voltage 150 v rms for rated mains voltage 300 v rms for rated mains voltage 450 v rms for rated mains voltage 600 v rms for rated mains voltage 1000 v rms i C iv i C iv i C iii i C iii i C iv i C iv i C iv i C iv i C iii climatic classifi cation 55/100/21 55/100/21 pollution degree (din vde 0110/1.89) 2 2 maximum working insulation voltage v iorm 891 1140 v peak input to output test voltage, method b* v iorm x 1.875 = v pr , 100% production test with t m = 1 sec, partial discharge < 5 pc v pr 1671 2137 v peak input to output test voltage, method a* v iorm x 1.6 = v pr , type and sample test, t m = 10 sec, partial discharge < 5 pc v pr 1426 1824 v peak highest allowable overvoltage (transient overvoltage t ini = 60 sec) v iotm 6000 8000 v peak safety-limiting values C maximum values allowed in the event of a failure. case temperature input current output power t s i s, input p s, output 175 230 600 175 230 600 c ma mw insulation resistance at t s , v io = 500 v r s >10 9 >10 9 ? * refer to the optocoupler section of the isolation and control components designers catalog, under product safety regulation s section, (iec/en/ din en 60747-5-2) for a detailed description of method a and method b partial discharge test profi les. note: these optocouplers are suitable for safe electrical isolation only within the safety limit data. maintenance of the safety da ta shall be ensured by means of protective circuits. surface mount classifi cation is class a in accordance with cecc 00802.
5 table 2. insulation and safety related specifi cations parameter symbol acpl-p343 acpl-w343 units conditions minimum external air gap (external clearance) l(101) 7.0 8.0 mm measured from input terminals to output terminals, shortest distance through air. minimum external tracking (external creepage) l(102) 8.0 8.0 mm measured from input terminals to output terminals, shortest distance path along body. minimum internal plastic gap (internal clearance) 0.08 0.08 mm through insulation distance conductor to conductor, usually the straight line distance thickness between the emitter and detector. tracking resistance (comparative tracking index) cti >175 >175 v din iec 112/vde 0303 part 1 isolation group iiia iiia material group (din vde 0110, 1/89, table 1) notes: 1. all avago data sheets report the creepage and clearance inherent to the optocoupler component itself. these dimensions are n eeded as a starting point for the equipment designer when determining the circuit insulation requiremen ts. however, once mounted on a printed circu it board, minimum creepage and clearance requirements must be met as specifi ed for individual equipment standards. for creepage, the shortest distance path along the surface of a printed circuit board between the solder fi llets of the input and output leads must be considered (the recommended land pattern does not necessarily meet the minimum creepage of the device). there are recommended techniques such as grooves an d ribs which may be used on a printed circuit board to achieve desired creepage and clearances. creepage and clearance distances will also c hange depending on factors such as pollution degree and insulation level. table 3. absolute maximum ratings parameter symbol min. max. units note storage temperature t s -55 125 c operating temperature t a -40 105 c output ic junction temperature t j 125 c average input current i f(avg) 25 ma 1 peak transient input current (<1 ? s pulse width, 300 pps) i f(tran) 1a reverse input voltage v r 5v high peak output current i oh(peak) 4.0 a 2 low peak output current i ol(peak) 4.0 a 2 total output supply voltage (v cc - v ee ) 035v input current (rise/fall time) t r(in) / t f(in) 500 ns output voltage v o(peak) -0.5 v cc v output ic power dissipation p o 700 mw 3 total power dissipation p t 745 mw 4 lead solder temperature 260 c for 10 sec., 1.6 mm below seating plane table 4. recommended operating conditions parameter symbol min. max. units note operating temperature t a -40 105 c output supply voltage (v cc - v ee )1530v input current (on) i f(on) 716ma input voltage (off) v f(off) -3.6 0.8 v
6 table 5. electrical specifi cations (dc) unless otherwise noted, all typical values are at t a = 25 c, v cc - v ee = 30 v, v ee = ground; all minimum and maximum specifi cations are at recommended operating conditions (t a = -40 to 105 c, i f(on) = 7 to 16 ma, v f(off) = -3.6 to 0.8 v, v ee = ground, v cc = 15 to 30 v). parameter symbol min. typ. max. units test conditions fig. note high level peak output current i oh -1.0 -2.8 a v o = v cc C 4 v 3, 4, 20 5 -3.0 a v cc - v o 15 v 6 low level peak output current i ol 1.0 3.5 a v o = v ee + 2.5 v 6, 7, 21 5 3.0 a v o - v ee 15 v 7 high output transistor rds(on) r ds,oh 1.4 2.5 ? i oh = -3.0 a 88 low output transistor rds(on) r ds,ol 0.6 1.5 ? i ol = 3.0 a 98 high level output voltage v oh vcc C 0.3 vcc C 0.2 v i o = -100 ma 2, 4, 22 9, 10 high level output voltage v oh vcc v i o = 0 ma, i f = 10 ma 1 low level output voltage v ol 0.1 0.2 v i o = 100 ma 5, 7, 23 high level supply current i cch 1.9 3.0 ma r g = 10 ? , c g = 25 nf, i f = 10 ma 10, 11 low level supply current i ccl 1.9 3.0 ma r g = 10 ? , c g = 25 nf, v f = 0 v threshold input current low to high i flh 1.5 4.0 ma r g = 10 ? , c g = 25 nf, v o > 5 v 12, 13, 24 threshold input voltage high to low v fhl 0.8 v input forward voltage v f 1.2 1.55 1.95 v i f = 10 ma 19 temperature coeffi cient of input forward voltage ? v f / ? t a -1.7 mv/c i f = 10 ma input reverse breakdown voltage bv r 5v i r = 100 ? a input capacitance c in 70 pf f = 1 mhz, v f = 0 v uvlo threshold v uvlo+ 12.1 12.8 13.5 v v o > 5 v, i f = 10 ma 25 v uvlo- 11.1 11.8 12.4 uvlo hysteresis uvlo hys 1.0 v
7 table 6. switching specifi cations (ac) unless otherwise noted, all typical values are at t a = 25 c, v cc - v ee = 30 v, v ee = ground; all minimum and maximum specifi cations are at recommended operating conditions (t a = -40 to 105 c, i f(on) = 7 to 16 ma, v f(off) = -3.6 to 0.8 v, v ee = ground, v cc = 15 to 30 v). parameter symbol min. typ. max. units test conditions fig. note propagation delay time to high output level t plh 50 98 200 ns r g = 10 ? , c g = 25 nf, f = 20 khz, duty cycle = 50%, i f = 7 ma to 16 ma, v cc = 15 v to 30 v 14, 15, 16, 17, 18, 26 propagation delay time to low output level t phl 50 95 200 ns pulse width distortion pwd 22 70 ns 11 propagation delay diff erence between any two parts pdd (t phl - t plh ) -100 100 ns 33, 34 12 rise time t r 43 ns vcc = 30 v 26 fall time t f 40 ns output high level common mode transient immunity |cm h |3550 kv/ ? s t a = 25 c, i f = 10 ma, v cc = 30 v, v cm = 1500 v with split resistors 27 13, 14 output low level common mode transient immunity |cm l | 35 50 kv/ ? s t a = 25 c, v f = 0 v, v cc = 30 v, v cm = 1500 v with split resistors 13, 15 table 7. package characteristics unless otherwise noted, all typical values are at t a = 25 c; all minimum/maximum specifi cations are at recommended operating conditions. parameter symbol device min. typ. max. units test conditions fig. note input-output momentary withstand voltage* v iso acpl-p343 3750 v rms rh < 50%, t = 1 min., t a = 25 c 16,18 acpl-w343 5000 v rms rh < 50%, t = 1 min., t a = 25 c 17,18 input-output resistance r i-o >50 12 ? v i-o = 500 v dc 18 input-output capacitance c i-o 0.6 pf f =1 mhz led-to-ambient thermal resistance r 11 135 c/w 19 led-to-detector thermal resistance r 12 27 detector-to-led thermal resistance r 21 39 detector-to-ambient thermal resistance r 22 47 * the input-output momentary withstand voltage is a dielectric voltage rating that should not be interpreted as an input-outpu t continuous voltage rating. for the continuous voltage rating, refer to your equipment level safety specifi cation or avago technologies application note 1074 entitled optocoupler input-output endurance voltage.
8 notes: 1. derate linearly above 70 c free-air temperature at a rate of 0.3 ma/c. 2. maximum pulse width = 10 ? s. this value is intended to allow for component tolerances for designs with i o peak minimum = 3.0 a. see applications section for additional details on limiting i oh peak. 3. derate linearly above 85 c free-air temperature at a rate of 16.9 mw/c . 4. derate linearly above 85 c free-air temperature at a rate of 15.3 mw/c . the maximum led junction temperature should not exceed 125 c. 5. maximum pulse width = 50 ? s. 6. output is sourced at -3.0 a with a maximum pulse width = 10 ? s. v cc -v o is measured to ensure 15 v or below. 7. output is sourced at 3.0 a with a maximum pulse width = 10 ? s. v o -v ee is measured to ensure 15 v or below. 8. output is sourced at -3.0 a/3.0 a with a maximum pulse width = 10 ? s. 9. in this test v oh is measured with a dc load current. when driving capacitive loads, v oh will approach v cc as i oh approaches zero amps. 10. maximum pulse width = 1 ms. 11. pulse width distortion (pwd) is defi ned as |t phl -t plh | for any given device. 12. the diff erence between t phl and t plh between any two acpl-p343 parts under the same test condition. 13. pin 2 needs to be connected to led common. 14. common mode transient immunity in the high state is the maximum tolerable dv cm /dt of the common mode pulse, v cm , to assure that the output will remain in the high state (i.e., v o > 15.0 v). 15. common mode transient immunity in a low state is the maximum tolerable dv cm /dt of the common mode pulse, v cm , to assure that the output will remain in a low state (i.e., v o < 1.0 v). 16. in accordance with ul1577, each optocoupler is proof tested by applying an insulation test voltage 4500 v rms for 1 second (leakage detection current limit, i i-o < 5 ? a). 17. in accordance with ul1577, each optocoupler is proof tested by applying an insulation test voltage 6000 v rms for 1 second (leakage detection current limit, i i-o < 5 ? a). 18. device considered a two-terminal device: pins 1, 2, and 3 shorted together and pins 4, 5 and 6 shorted together. 19. the device was mounted on a high conductivity test board as per jedec 51-7
9 figure 1. high output rail voltage vs. temperature figure 2. v oh vs. temperature figure 3. i oh vs. temperature figure 4. i oh vs. v oh figure 5.v ol vs. temperature figure 6. i ol vs. temperature i f = 1 0 m a i out = 0 m a v cc = 3 0 v v ee = 0 v i f = 7 t o 16 m a i out = -1 00 m a v cc = 15 t o 3 0 v v ee = 0 v i f = 7 t o 16 m a v out = v cc ? 4 v v cc = 15 t o 3 0 v v ee = 0 v i f = 7 t o 16 m a v cc = 15 t o 3 0 v v ee = 0 v t a = 25 c v f (off) = 0 v i out = 1 00 m a v cc = 15 t o 3 0 v v ee = 0 v 2 9.8 4 2 9.8 1 2 9.8 2 2 9.8 3 2 9.77 2 9.78 2 9.79 2 9.8 -4 0 -3 0 -2 0 -1 00 1 0 2 0 3 0 4 0 5 0 6 0708090 1 00 v oh - hi g h out p ut r ail volta g e - v t a - te mp e r atu r e - c -4 0 -3 0 -2 0 -1 00 1 0 2 0 3 0 4 0 5 0 6 0708090 1 00 t a - te mp e r atu r e - c -4 0 -3 0 -2 0 -1 00 1 0 2 0 3 0 4 0 5 0 6 0708090 1 00 t a - te mp e r atu r e - c -4 0 -3 0 -2 0 -1 00 1 0 2 0 3 0 4 0 5 0 6 0708090 1 00 t a - te mp e r atu r e - c -4 0 -3 0 -2 0 -1 00 1 0 2 0 3 0 4 0 5 0 6 0708090 1 00 t a - te mp e r atu r e - c 0 - 0. 15 - 0. 1 - 0.0 5 - 0. 25 - 0. 2 (v oh -v cc ) - hi g h out p ut volta g e d r o p - v - 0. 5 0 -2 -1 . 5 -1 -4 -3 . 5 -3 -2 . 5 i oh - out p ut hi g h cu rr ent - a -1 - 0. 5 0 0. 5 -3 -2 . 5 -2 -1 . 5 -4 . 5 -4 -3 . 5 0 123456 i oh - out p ut hi g h cu rr ent - a (v oh -v cc ) - hi g h out p ut volta g e d r o p - v 0. 1 0. 12 0. 14 0.0 2 0.0 4 0.0 6 0.08 0 v ol - out p ut low volta g e - v 3 3 . 5 4 4 . 5 0. 5 1 1 . 5 2 2 . 5 0 i ol - out p ut low cu rr ent - a v f (off) = 0 v v out = 2 . 5 v v cc = 15 t o 3 0 v v ee = 0 v
10 figure 7. i ol vs. v ol figure 8. r ds,oh vs. temperature figure 9. r ds,ol vs. temperature figure 11. i cc vs. v cc figure 12. i flh hysteresis figure 10. i cc vs. temperature i f = 7 t o 16 m a i out = -3 a v cc = 15 t o 3 0 v v ee = 0 v 3 3 . 5 4 4 . 5 5 0. 5 1 1 . 5 2 2 . 5 3 0 00. 511 . 52 3 2 . 5 i ol - out p ut low cu rr ent - a v ol - out p ut low volta g e - v v f (off) = 0 v v cc = 15 t o 3 0 v v ee = 0 v t a = 25 c 2 2 . 5 0. 5 1 1 . 5 0 r d s ,oh - hi g h out p ut t r an s i s to r r d s (on) - 7 -4 0 -3 0 -2 0 -1 00 1 0 2 0 3 0 4 0 5 0 6 0708090 1 00 t a - te mp e r atu r e - c 0.7 0.8 0.9 1 0. 2 0. 3 0. 4 0. 5 0. 6 0 0. 1 r d s ,ol - low out p ut t r an s i s to r r d s (on) - 7 -4 0 -3 0 -2 0 -1 00 1 0 2 0 3 0 4 0 5 0 6 0708090 1 00 t a - te mp e r atu r e - c -4 0 -3 0 -2 0 -1 00 1 0 2 0 3 0 4 0 5 0 6 0708090 1 00 t a - te mp e r atu r e - c v f (off) = 0 v i out = 3 a v cc = 15 t o 3 0 v v ee = 0 v 2 2 . 5 0. 5 1 1 . 5 i cc - s u pp ly cu rr ent - m a 0 i f = 1 0 m a f or i cch v f = 0 v f or i ccl v cc = 3 0 v v ee = 0 v i cch i ccl 2 2 . 5 0. 5 1 1 . 5 i cc - s u pp ly cu rr ent - m a 0 15 2 0 25 3 0 v cc - s u pp ly volta g e - v i ccl i cch i f = 1 0 m a f or i cch v f = 0 v f or i ccl t a = 25 c v ee = 0 v t a = 25 c v cc = 3 0 v v ee = 0 v i flh on i flh off 24 2 9 34 4 9 14 1 9 v o - out p ut volta g e - v -1 4 i flh - low to hi g h cu rr ent th r e s hold - m a 00. 511 . 52 3 2 . 5
11 figure 13. i flh vs. temperature figure 14. propagation delays vs. v cc figure 15. propagation delays vs. i f figure 17. propagation delay vs. rg figure 18. propagation delay vs. cg figure 16. propagation delays vs. temperature i f = 7 m a v cc = 3 0 v, v ee = 0 v r g = 1 0 7 , c g = 25 nf duty cycle = 5 0 % f = 2 0 khz i f = 7 m a, t a = 25 c v cc = 3 0 v, v ee = 0 v r g = 1 0 7 duty cycle = 5 0 % f = 2 0 khz i f = 7 m a, t a = 25 c v cc = 3 0 v, v ee = 0 v c g = 25 nf duty cycle = 5 0 % f = 2 0 khz 1 . 6 1 .8 2 2 . 2 2 . 4 0. 2 0. 6 0. 4 0.8 1 1 . 2 1 . 4 0 i flh - low to hi g h cu rr ent th r e s hold - m a -4 0 -3 0 -2 0 -1 00 1 0 2 0 3 0 4 0 5 0 6 0708090 1 00 t a - te mp e r atu r e - c v cc = 15 t o 3 0 v v ee = 0 v i flh on i flh off 1 00 11 0 12 0 70 80 90 6 0 t p - pr o p a g ation delay - ns 15 2 0 25 3 0 v cc - s u pp ly volta g e - v i f = 7 m a t a = 25 c r g = 1 0 7 , c g = 25 nf duty cycle = 5 0 % f = 2 0 khz t p lh t p hl t p lh t p hl t p lh t p hl t p lh t p hl 1 00 11 0 12 0 70 80 90 6 0 6 8 1 0 12 14 16 t p - pr o p a g ation delay - ns i f - fo r wa r d led cu rr ent - m a 1 00 11 0 12 0 70 80 90 6 0 t p - pr o p a g ation delay - ns 90 9 5 1 00 1 0 5 65 70 7 5 80 8 5 6 0 65 1 0 15 2 0 25 3 0 35 4 0 45 5 0 1 0 15 2 0 25 3 0 35 4 0 45 5 0 t p - pr o p a g ation delay - ns r g - s e r ie s load r e s i s tance - 7 9 5 1 00 1 0 5 11 0 70 7 5 80 8 5 90 6 0 65 t p - pr o p a g ation delay - ns c g - s e r ie s load ca p acitance - nf -4 0 -3 0 -2 0 -1 00 1 0 2 0 3 0 4 0 5 0 6 0708090 1 00 t a - te mp e r atu r e - c v cc = 3 0 v, v ee = 0 v t a = 25 c r g = 1 0 7 , c g = 25 nf duty cycle = 5 0 % f = 2 0 khz t p lh t p hl
12 figure 19. input current vs. forward voltage figure 20. i oh test circuit figure 21. i ol test circuit 1 m f i f = 7 t o 16 m a + _ + _ 2 . 5 v p uls ed v cc = 15 t o 3 0 v 1 m f i ol 1 00 1 1 0 0. 1 1 . 41 . 45 1 . 51 . 55 1 . 61 . 65 i f - fo r wa r d cu rr ent - m a v f - fo r wa r d volta g e - v 1 2 3 6 5 4 + _ + _ 4 v p uls ed v cc = 15 t o 3 0 v i oh 1 2 3 6 5 4
13 figure 22. v oh test circuit figure 23. v ol test circuit figure 24. i flh test circuit 1 2 3 6 5 4 + _ 1 00 m a v cc = 15 t o 3 0 v 1 m f v oh i f = 7 t o 16 m a 1 00 m a + _ v cc = 15 t o 3 0 v v ol 1 m f i f v o > 5 v v cc = 15 t o 3 0 v 1 m f 1 0 7 25 nf + _ 1 2 3 6 5 4 1 2 3 6 5 4
14 figure 25. uvlo test circuit figure 26. t phl , t phl , t r and t f test circuit and waveforms figure 27. cmr test circuit with split resistors network and waveforms 1 2 3 6 5 4 + _ 1 m f v o > 5 v i f = 7 t o 16 m a v cc v o v cc = 15 t o 3 0 v 1 m f 1 0 7 25 nf + _ 1 2 3 6 5 4 i f = 7 t o 16 m a, 2 0 khz, 5 0 % duty cy c l e 10 ma 10 ma 1 0 m a v cc = 3 0 v v o + _ 1 m f + _ v c m = 15 00 v 5 v 2 0 5 7 13 7 7 + _ 1 2 3 6 5 4
15 application information product overview description the acpl-p343/w343 is an optically isolated power output stage capable of driving igbts of up to 200 a and 1200 v. based on bcdmos technology, this gate drive optocou- pler delivers higher peak output current, better rail-to-rail output voltage performance and two times faster speed than the previous generation products. the high peak output current and short propagation delay are needed for fast igbt switching to reduce dead time and improve system overall effi ciency. rail-to-rail output voltage ensures that the igbts gate voltage is driven to the optimum intended level with no power loss across igbt. this helps the designer lower the system power which is suitable for bootstrap power supply operation. it has very high cmr( common mode rejection) rating which allows the microcontroller and the igbt to operate at very large common mode noise found in industrial motor drives and other power switching applications. the input is driven by direct led current and has a hysteresis that prevents output oscillation if insuffi cient led driving current is applied. this will eliminates the need of addi- tional schmitt trigger circuit at the input led. the stretched so6 package which is up to 50% smaller than conventional dip package facilitates smaller more compact design. these stretched packages are compliant to many industrial safety standards such as iec/en/din en 60747-5-2, ul 1577 and csa. recommended application circuit the recommended application circuit shown in figure 28 illustrates a typical gate drive implementation using the acpl-p343. the following describes about driving igbt. however, it is also applicable to mosfet. designers will need to adjust the v cc supply voltage, depending on the mosfet or igbt gate threshold requirements (recom- mended v cc = 15 v for igbt and 12 v for mosfet). the supply bypass capacitors (1 ? f) provide the large transient currents necessary during a switching transition. because of the transient nature of the charging currents, a low current (3.0 ma) power supply will be enough to power the device. the split resistors (in the ratio of 1.5:1) across the led will provide a high cmr response by providing a balanced resistance network across the led. the gate resistor rg serves to limit gate charge current and controls the igbt collector voltage rise and fall times. in pc board design, care should be taken to avoid routing the igbt collector or emitter traces close to the acpl-p343 input as this can result in unwanted coupling of transient signals into acpl-p343 and degrade performance. _ v ee cathode nc anode v out v cc _ r r + 1 2 3 6 5 4 r g + v ce + hvdc -hvdc 3-hvdc ac 1 m f v cc = 15 v v ee = 5 v + _ q1 q2 _ + v ce _ + _ figure 28. recommended application circuit with split resistors led drive
16 rail-to-rail output figure 29 shows a typical gate drivers high current output stage with 3 bipolar transistors in darlington confi guration. during the output high transition, the output voltage rises rapidly to within 3 diode drops of v cc . to ensure the v out is at v cc in order to achieve igbt rated v ce(on) voltage. the level of v cc will be need to be raised to beyond v cc +3(v be ) to account for the diode drops. and to limit the output voltage to v cc , a pull-down resistor, r pull-down between the output and v ee is recommended to sink a static current while the output is high. figure 29. typical gate driver with output stage in darlington confi guration figure 30. acpl-p343/w343 with pmos and nmos output stage for rail-to-rail output voltage 1 2 3 4 8 7 6 5 v cc v out v ee cathode nc anode nc r g r p ull-down acpl-p343 uses a power pmos to deliver the large current and pull it to v cc to achieve rail-to-rail output voltage as shown in figure 30. this ensures that the igbts gate voltage is driven to the optimum intended level with no power loss across igbt even when an unstable power supply is used. v cc v ee 1 2 3 6 5 4 cathode nc anode v out
17 selecting the gate resistor (rg) step 1: calculate rg minimum from the i ol peak specifi cation. the igbt and rg in figure 28 can be analyzed as a simple rc circuit with a voltage supplied by acpl-p343/w343. rg v cc C v ee C v ol i olpeak = 15 v + 5 v C 2.9 v 4a = 4.3 ? ? 5 ? the v ol value of 2.9 v in the previous equation is the v ol at the peak current of 4.0 a (see figure 7). step 1: check the acpl-p343/w343 power dissipation and increase rg if necessary. the acpl-p343/w343 total power dissipation (p t ) is equal to the sum of the emitter power (p e ) and the output power (p o ). p t = p e + p o p e = i f ? v f ? duty cycle p o = p o(bias) + p o(switching) = i cc ? (v cc -v ee ) + e sw (rg;cg) ? f using i f (worst case) = 16 ma, rg = 5 ? , max duty cycle = 80%, cg = 25 nf, f = 25 khz and t a max = 85 c: p e = 16 ma ? 1.95 v ? 0.8 = 25 mw p o = 3 ma ? 20 v + 5 ? j ? 25 khz = 60 mw + 125 mw = 185 mw < 700 mw (p o(max) @ 85 c) the value of 3 ma for i cc in the previous equation is the maximum i cc over the entire opera ting temperature range. since p o is less than p o(max) , rg = 5 ? is alright for the power dissipation. figure 31. energy dissipated in the acpl-p343/w343 for each igbt switching cycle 2 .0 e- 0 5 2 . 5e- 0 5 3 .0 e- 0 5 1 .0 e- 0 5 1 . 5e- 0 5 0.0 e+ 00 5 .0 e- 0 6 e s w - ene rg y p e r s witchin g cycle - j 0 246 8 1 0 r g - ga t e re s i st a n ce - 7 v cc = 3 0 v v cc = 2 0 v v cc = 15 v
18 led drive circuit considerations for high cmr performance figure 32 shows the recommended drive circuit for the acpl-p343/w343 that gives optimum common-mode rejection. the two current setting resistors balance the common mode impedances at the leds anode and cathode. common-mode transients can be capacitive coupled from the led anode, through c la (or cathode through c lc ) to the output-side ground causing current to be shunted away from the led (which is not wanted when the led should be on) or conversely cause current to be injected into the led (which is not wanted when the led should be off ). table 8 shows the directions of i lp and i ln depend on the polarity of the common-mode transient. for transients occurring when the led is on, common-mode rejection (cm h , since the output is at high state) depends on led current (i f ). for conditions where i f is close to the switching threshold (i flh ), cm h also depends on the extent to which i lp and i ln balance each other. in other words, any condition where a common-mode transient causes a momentary decrease in i f (i.e. when dv cm /dt > 0 and |i lp | > |i ln |, referring to table 8) will cause a common- mode failure for transients which are fast enough. likewise for a common-mode transient that occurs when the led is off (i.e. cm l , since the output is at low state), if an imbalance between i lp and i ln results in a transient i f equal to or greater than the switching threshold of the optocoupler, the transient signal may cause the output to spike above 1 v, which constitutes a cm l failure. the balanced i led -setting resistors help equalize the common mode voltage change at the anode and cathode. the shunt drive input circuit will also help to achieve high cm l performance by shunting the led in the off state. +5 v r 1 r 2 v cc v ee 1 2 3 6 5 4 cathode anode v out i l p i ln c la c lc v dd = 5 .0 v: r 1 = 2 0 5 7 1% r 2 = 13 7 7 1% r 1 / r 2 1 . 5 figure 32. recommended high-cmr drive circuit for the acpl-p343/w343 table 8. common mode pulse polarity and led current transients dv cm /dt i lp direction i lp direction if |i lp | < |i ln |, i f is momentarily if |i lp | > |i ln |, i f is momentarily positive (>0) away from led anode through c la away from led cathode through c lc increase decrease negative(<0) toward led anode through c la toward led cathode through c lc decrease increase
19 dead time and propagation delay specifi cations the acpl-p343/w343 includes a propagation delay dif- ference (pdd) specifi cation intended to help designers minimize dead time in their power inverter designs. dead time is the time period during which both the high and low side power transistors (q1 and q2 in figure 28) are off . any overlap in q1 and q2 conduction will result in large currents fl owing through the power devices between the high and low voltage motor rails. to minimize dead time in a given design, the turn on of led2 should be delayed (relative to the turn off of led1) so that under worst-case conditions, transistor q1 has just turned off when transistor q2 turns on, as shown in figure 33. the amount of delay necessary to achieve this condition is equal to the maximum value of the propa- gation delay diff erence specifi cation, pdd max , which is specifi ed to be 100 ns over the operating temperature range of 40 c to 105 c. delaying the led signal by the maximum propagation delay diff erence ensures that the minimum dead time is zero, but it does not tell a designer what the maximum dead time will be. the maximum dead time is equivalent to the diff erence between the maximum and minimum propagation delay diff erence specifi cations as shown in figure 34. the maximum dead time for the acpl-p343/ w343 is 200 ns (= 100 ns C (-100 ns)) over an operating temperature range of -40 c to 105 c. note that the propagation delays used to calculate pdd and dead time are taken at equal temperatures and test conditions since the optocouplers under consideration are typically mounted in close proximity to each other and are switching identical igbts. figure 33. minimum led skew for zero dead time figure 34. waveforms for dead time
for product information and a complete list of distributors, please go to our web site: www.avagotech.com avago, avago technologies, and the a logo are trademarks of avago technologies in the united states and other countries. data subject to change. copyright ? 2005-2011 avago technologies. all rights reserved. av02-2928en - november 14, 2011 led current input with hysteresis the detector has optical receiver input stage with built in schmitt trigger to provide logic compatible waveforms, eliminating the need for additional wave shaping. the hysteresis (figure 12) provides diff erential mode noise immunity and minimizes the potential for output signal chatter. under voltage lockout the acpl-p343/w343 under voltage lockout (uvlo) feature is designed to prevent the application of insuffi - cient gate voltage to the igbt by forcing the acpl-p343/ w343 output low during power-up. igbts typically require gate voltages of 15 v to achieve their rated v ce(on) voltage. at gate voltages below 13 v typically, the v ce(on) voltage increases dramatically, especially at higher currents. at very low gate voltages (below 10 v), the igbt may operate in the linear region and quickly overheat. the uvlo function causes the output to be clamped whenever insuffi cient operating supply (v cc ) is applied. once v cc exceeds v uvlo+ (the positive-going uvlo threshold), the uvlo clamp is released to allow the device output to turn on in response to input signals. thermal model for acpl-p343/w343 stretched so6 package optocoupler defi nitions: r 11 : junction to ambient thermal resistance of led due to heating of led r 12 : junction to ambient thermal resistance of led due to heating of detector (output ic) r 21 : junction to ambient thermal resistance of detector (output ic) due to heating of led. r 22 : junction to ambient thermal resistance of detector (output ic) due to heating of detector (output ic). p 1 : power dissipation of led (w). p 2 : power dissipation of detector / output ic (w). t 1 : junction temperature of led (c). t 2 : junction temperature of detector (c). t a : ambient temperature. ambient temperature: junction to ambient thermal re- sistances were measured approximately 1.25 cm above optocoupler at ~23 c in still air thermal resistance c/w r 11 135 r 12 27 r 21 39 r 22 47 this thermal model assumes that an 6-pin single-channel plastic package optocoupler is soldered into a 7.62 cm x 7.62 cm printed circuit board (pcb) per jedec standards. the temperature at the led and detector junctions of the optocoupler can be calculated using the equations below. t 1 = (r 11 * p 1 + r 12 * p 2 ) + t a (1) t 2 = (r 21 * p 1 + r 22 * p 2 ) + t a (2) using the given thermal resistances and thermal model formula in this datasheet, we can calculate the junction temperature for both led and the output detector. both junction temperature should be within the absolute maximum rating. for example, given p 1 = 25 mw, p 2 = 185 mw, ta = 85 c: led junction temperature, t 1 = (r 11 * p 1 + r 12 * p 2 ) + t a = (135 * 0.025 + 27 * 0.185) + 85 = 93.4 c output ic junction temperature, t 2 = (r 21 * p 1 + r 22 * p 2 ) + t a = (39 *0.025 + 47 * 0.185) + 85 = 94.7 c t 1 and t 2 should be limited to 125 c based on the board layout and part placement. related application noted an5336 C gate drive optocoupler basic design for igbt/ mosfet an1043 C common-mode noise: sources and solutions av02-0310en C plastics optocouplers product esd and moisture sensitivity

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